1. Field of the Invention
The present invention relates to a sample/hold apparatus which may mainly apply to a liquid crystal driving circuit provided in a liquid crystal display.
2. Description of the Related Art
A typical sample/hold circuit provided in a liquid crystal driving circuit known by the inventors of the present application is arranged to have a sampling gate connected to a common input bus, a transfer gate connected to the sampling gate, a buffer amplifier connected to the transfer gate, a sampling capacitor connected to a line between the sampling gate and the transfer gate and a holding capacitor connected to a line between the transfer gate and the buffer amplifier. In operation, when a sampling signal is applied to the sampling gate, the sampling gate operates to open on the timing indicated by the sampling signal. Each time it is open, analog data is transferred from the input bus to the sampling capacitor. When a transfer signal is applied to the transfer gate, the transfer gate operates to open on the timing indicated by the transfer signal. Each time the transfer gate opens, the analog data held in the sampling capacitor is transferred to the holding capacitor, from which the analog data is sent to the buffer amplifier. The buffer amplifier serves to amplify the analog data and supply the resulting signal as an output for driving the liquid crystal.
Two or more of the known sample/hold circuits are typically connected to the input bus.
As shown in FIG. 1, when the sampling signal Sn falls, the sampling gate SGn operates to open. Then, after a time has passed when the analog data can be held in the sampling capacitor CSn, the sampling signal Sn rises, the sampling gate operates to close. However, the sampling capacitor may hold such a historical voltage as causing a voltage to be abruptly charged or discharged when the sampling gate changes from a close state to an open state. The abrupt charge or discharge may have an adverse effect such as noises on the input bus.
At the timing when the sampling gate starts to close as shown in FIG. 1, another sampling signal Sn+1 (to be applied to the adjacent sample/hold circuit connected to the input bus) falls, when the sampling gate SGn+1 operates to open. As such, the voltage charged in the sampling capacitor CSn+1 may causes noises to appear on the input bus, thereby allowing the noises to be charged in the sampling capacitor CSn. This results in disallowing the sampling capacitor CSn to read the original analog data, thereby impairing the accuracy on signal transmission.
As has been easily understood from the above description, the component indicated by the subscript "n+1" means a signal adjacent to the signal with a subscript "n".